In order to build an integrated circuit, many active devices need to be fabricated on a single substrate. The current practice in semiconductor manufacturing is to use thin film fabrication techniques. A large variety of materials can be deposited using thin films, including metals, semiconductors, insulators and the like. The composition and uniformity of these thin layers must be strictly controlled to facilitate etching of submicron features. The surface of the substrate, most often a wafer, must be planarized in some way to prevent the surface topography from becoming increasingly rough with each added thin film level. The formation of such films is accomplished by a large variety of techniques.
Chemical vapor deposition (CVD) processes are often selected over competing deposition techniques because they offer numerous advantages, including the ability of CVD to deposit films from a wide variety of chemical compositions.
In general a CVD process includes the following steps: a selected composition and flow rate of reactant and inert gases are dispatched into a reaction chamber; the gases move to the substrate surface; the reactants are adsorbed on the substrate surface; the species undergo a film-forming chemical reaction and the by-products of the reaction are desorbed from the surface and conveyed away from the surface.
The semiconductor industry's continuing drive towards tighter device geometries, has placed an increased demand for cost-effective solutions for the problem of planarization. TEOS-based oxides (tetraethylorthosilicate) have attracted the industry's attention for several years due to the superior film quality they offer over traditional silane-based CVD technologies. The TEOS/O3 processes operating at atmospheric pressures possess markedly superior step coverage and planarization characteristics. The unique high mobility of the low temperature TEOS chemistry provides excellent planarization for sub-half micron geometries. As a result there has been an increased use of TEOS/ozone chemistry. The TEOS is used as a source of silicon to deposit silicon dioxide (SiO2).
TEOS/O3 is almost always deposited via atmospheric pressure chemical vapor deposition (APCVD) or nearly atmospheric pressures, using sub atmospheric chemical vapor deposition (SACVD). TEOS/ozone APCVD possesses a number of desirable characteristics, including: it is capable of sub-half micron void-free gap filling with good planarization, it offers a low deposition temperature, high moisture resistance, low stress, high breakdown voltage, low leakage current and low particle densities.
A TEOS molecule is fairly large and complex, has a low sticking coefficient and yields better step coverage than other silicon sources. It is found that a TEOS molecule can actually move over several microns before it finally settles down to react with the other species. Less reactive ozone (O3), in TEOS/O3 applications, allows even more surface mobility, by permitting the TEOS molecule to move over even longer distances before it reacts.
Other benefits of TEOS/ozone include: flow-like, as-deposited step coverage, lower reflow temperatures with excellent stability, and lower particle counts.
Although ozone based TEOS processes for undoped and doped SiO2 films have been developed for high aspect ratio gapfill applications. One of the major issues facing integration of these films into standard process flows in semiconductor fabrication has to do with large shifts in high frequency capacitance voltage (C-V) flat band voltage due to fixed charge in the films.
The fixed charge is located in the so-called transition region between silicon (Si) and SiO2. These charges are named fixed charges because they do not change their charge state by exchange of mobile carriers with the silicon, as with the interface trap charge. The fixed charge is considered to be a sheet of charge at the Si/SiO2 interface.
The value of the fixed charge is determined by measuring the voltage shift of a high frequency capacitance-voltage (C-V) curve of a MOS capacitor test device. For the case of fixed charge at the interface, the flat-band voltage, of the C-V curve is related to the oxide charge, oxide thickness, and work function difference between the gate electrode and the silicon.
The value of the fixed charge depends on the oxidizing ambient, oxidizing temperature, silicon orientation, cooling rate from elevated temperature, cooling ambient, and subsequent anneal cycles. Although, it is desirable to minimize the value of the fixed charge, current semiconductor manufacturing technologies use ion implantation to control the device threshold voltage, which is the device parameter most impacted by the fixed charge. In spite of the ability to override small variations in the fixed charge, a goal of maintaining a low and reproducible value of the fixed charge is nevertheless still desirable during fabrication.
Fixed charge has generally been related to the presence of residual carbon in the films. It is believed that at higher pressures, due to high molecular collision frequency and increased recombination reactions, the number of oxygen atoms available for reaction is lower than at lower pressures. Any increase in O3 flow/concentration is met by lower life time of the O3 molecule leading to the saturation of atomic concentration of oxygen in the reaction chamber.
For lower pressure processes it has been shown that increasing the process temperature helps lower the fixed charge but this remedy is not totally effective for low pressure processes, such as TEOS/O3 APCVD.
What is still needed is a thin film fabrication process that reduces the fixed charge value in the deposited film.